1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a system for compensating response speed and a method of controlling frame data of an image in which response speed of a, liquid crystal can be increased by using an embedded frame memory, not an external frame memory.
2. Description of the Related Art
Recently, liquid crystal displays have been used as displays not only in personal computers but also in high-definition televisions. Accordingly, the response speed of a liquid crystal reacting according to applied image data voltage should be quick in order for the liquid crystal displays to operate well in a multimedia environment.
However, most liquid crystals have a response speed that is faster than the speed of receiving image data of 1 frame. For example, when data of 60 frames is displayed on a screen for 1 second, at least 16.6 ms is consumed for a liquid crystal panel to change to a liquid crystal state corresponding to the image data voltage. Accordingly, a circuit for compensating response speed is used.
A dynamic capacitance compensation (DCC) circuit is generally used as the circuit for compensating response speed. The DCC circuit improves the response speed of a liquid crystal by comparing voltages of a current image and a previous image, and outputting frame data of an image having a bigger or smaller gray voltage level than the current image based on the result of comparing the voltages.
FIG. 1 is a block diagram illustrating a prior art system 100 for compensating response speed. System 100 for compensating response speed includes a frame memory controller 110, a frame memory 120, and a circuit 130 for compensating response speed.
The frame memory controller 110 receives a current image Fn from an external graphic source (not shown) and transmits the current image Fn to the frame memory 120. Also, the frame memory controller 110 receives a previous image Fn−1 from the frame memory 120 and transmits the previous image Fn−1 to the circuit 130 for compensating response speed.
The frame memory 120, which is controlled by the frame memory controller 110, stores the current image Fn received from the frame memory controller 110 and outputs the previous image Fn−1 stored in the frame memory 120. The current image Fn and the previous image Fn−1 are images having only a temporal difference.
The frame memory 120 exists to supply the previous image Fn−1 to the circuit 130 for compensating response speed, and is formed of a chip B, which is different from a chip A forming the frame memory controller 110 and the circuit 130 for compensating response speed.
The circuit 130 for compensating response speed receives the current image Fn from the external graphic source and receives the previous image Fn−1 from the frame memory controller 110. The circuit 130 for compensating response speed compares voltages of the received current image Fn and the previous image Fn−1, and compensates the response speed of a liquid crystal correspondingly to the result of compared the voltages.
The circuit 130 for compensating response speed can be a DCC circuit that includes a look-up table for a changing gray voltage of the current image Fn.
A liquid crystal display processes data according to the speed of receiving the current image Fn. Meanwhile, as the definition of the current image Fn increases, the speed of receiving data also increases, and thus, as the definition of the current image Fn increases, the processing speed of the circuit 130 for compensating response speed should also increase. Consequently, as the definition increases, the operating speed and capacity of the frame memory 120 should increase. Accordingly, a system for compensating response speed using a compressing/restoring method has been developed.
FIG. 2 is a block diagram illustrating a system 200 for compensating response speed using a prior art compressing/restoring method.
The system 200 for compensating response speed using the prior art compressing/restoring method includes a frame memory controller 210, a frame memory 220, a circuit 230 for compensating response speed, an encoder 240, a first decoder 250, a second decoder 260, and a circuit 270 for restoring a previous image.
The encoder 240 generates a compressed current image F′n by compressing a current image Fn received from an external graphic source (not shown). The first decoder 250 generates a restored current image F″n by restoring the compressed current image F′n received from the encoder 240.
The frame memory controller 210 transmits the compressed current image F′n, received from the encoder 240, to the frame memory 220, and transmits a compressed previous image F′n−1, received from the frame memory 220, to the second decoder 260.
The second decoder 260 generates a restored previous image F″n−1 by restoring the compressed previous image F′n−1 received from the frame memory controller 210.
The circuit 270 for restoring a previous image generates a similar previous image F′″n−1 by receiving the current image Fn, the restored current image F″n, and the restored previous image F″n−1. The similar previous image F′″n−1 is an image from which noise of the restored previous image F″n−1 is removed.
The circuit 230 for compensating response speed compares voltages of the current image Fn and the similar previous image F′″n−1, changes a gray voltage of the current image Fn according to the result of comparing the voltages, and outputs the changed gray voltage of the current image Fn.
Meanwhile, using the prior art compressing/restoring method, the amount of image data that can be transmitted via the same data bus width increases, and, thus, the operating speed of the frame memory 220 can be increased. Also, since compressed data is stored in the frame memory 220, memory capacity can also be increased. The memory capacity can be increased more, by forming the frame memory 200 of a plurality of sub frame memories 220_1 through to 220_N.
However, the system 200 uses the external frame memory 220 formed of a separate chip, not a system on chip (SoC). As a result, as the number of sub frame memories 220_1 through to 220_N increases, the number of data bus pins required also increases.
When the number of data bus pins increases, the size of the entire system increases. Also, an RC delay, caused by an increase of a load cap between bus lines or between a bus line and a pin, also increases.